Course: digital system and simulation, VHDL lab

Course no. :n/a
ECTS credits:2.5
Lecturer(s):M.Sc. K. Schubert
Available: winter term summer term
Course type:Practical exercises
Exam type:Experimental study
Exam requirements:Successful participation in all lab experiments: preparation (theory),
computer-aided design and simulation, demonstration of the results
Objectives:The students are in command of simple FPGA/CPLD design environments and are able to familiarize themselves with complex design and simulation environments.
The form of the lab course with intensive and autonomous group work requires that the students deal with different communication and working styles in their groups. Accordingly, the students are able to independently apply the basics of classical project management, such as team organization, task planning and division of labor. In this way, they have trained social skills such as teamwork, criticism and communication skills. Furthermore, they have the competence to find solutions to problems and to select the right methods, to conduct research and independent acquisition of knowledge as well as to present and comprehensively document work results.
Course contents:Design and simulation of combinational and sequential circuits using VHDL only
Mixed mode design entry (using schematic editor and VHDL)
Examples of design entry and simulation using a complex design environment
Literature:Perry: VHDL Made easy
Handbücher der Firmen XILINX und Mentor Graphics/
Manuals of the companies XILINX and Mentor Graphics
available in modul:technical compulsory elective bachelor in semester 6